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Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F674
FEATURES
* 16-bit serial I/O shift register * 16-bit parallel-in/serial-out converter * Recirculating serial shifting * Common serial data I/O pin (3-State)
DESCRIPTION
The 74F674 is a 16-bit shift register with serial and parallel load capability and serial output. A single pin serves alternately as an input for serial entry or as a 3-State serial output. In the serial out mode the data recirculates in the register. Chip Select, Read/Write and Mode inputs provide control flexibility. The 74F674 operates in one of four modes, as indicated in the Function table. Hold: A High signal on the Chip Select (CS) input prevents clocking and forces the Serial Input/Output (SI/O) 3-State buffer into the high impedance state. Serial load: Data present on the SI/O pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks. Serial output: The SI/O 3-State buffer is active and the register contents are shifted out from Q15 and simultaneously shifted back into Q0. Parallel load: Data present on D0-D15 is entered into the register on the falling edge of CP. The SI/O 3-State buffer is active and represents the Q15 output. To prevent false clocking, CP must be Low during a Low-to-High transition of CS.
PIN CONFIGURATION
CS CP R/W NC M SI/O D0 D1 D2
1 2 3 4 5 6 7 8 9
24 VCC 23 D15 22 D14 21 D13 20 D12 19 D11 18 D10 17 D9 16 D8 15 D7 14 D6 13 D5
D3 10 D4 11 GND 12
SF01188
TYPE 74F674
TYPICAL fMAX 95MHz
TYPICAL SUPPLY CURRENT (TOTAL) 55mA
ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Slim DIP (300mil) 24-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F674N N74F674D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0-D15 CS CP M R/W SI/O Parallel data inputs Chip Select input (active Low) Clock Pulse input (active falling edge) Mode select input Read/Write input Serial data input or Serial 3-state output NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state. DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 70mA/0.6mA 3.0mA/24mA
1989 Feb 05
1
853-1248 92263
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F674
LOGIC SYMBOL
7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23
LOGIC SYMBOL (IEEE/IEC)
SRG16 5 0 1 0 M 3 & EN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 2 3 5 CS CP R/W M SO 7 8 VCC = Pin 24 GND = Pin 12 6 9
3
1 2
& C4(0/1/2)
3, 4D 3, 4D
3, 4D
SF01189
10 11 13
FUNCTION TABLE
CONTROL INPUTS CS H L L L H L X = = = = R/W X L H H M X X L H CP X SI/O STATUS High Z Data in Data out Active OPERATING MODE Hold Serial load Serial output with recirculation Parallel load; no shifting
14 15 16 17 18 19 20 21 22 23 6 3, 4D
High voltage level Low voltage level Don't care High-to-Low transition of designed input
SF01190
LOGIC DIAGRAM
D0-D15 (7-11, 13-23) M 5
CS
1 Q0
PE
D0-D15
Q15 CP 2 CP
6 SI/O
R/W VCC = GND = Pin 24 Pin 12
3
SF01191
1989 Feb 05
2
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F674
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5.0 -0.5 to +VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -3 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 MIN VOH High-level output voltage VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK SI/O only others VCC = MAX, VI = 5.5V VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V SI/O only VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX -60 55 10%VCC 5%VCC 10%VCC 5%VCC 2.4 2.7 3.3 0.35 0.35 -0.73 0.50 0.50 -1.2 100 100 20 -0.6 70 -600 -150 80 LIMITS TYP2 UNIT MAX V V V V V A A A mA A A mA mA
VOL VIK II IIH IIL IOZH+IIH IOZL+IIL IOS ICC
Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current High-level voltage applied Off-state output current Low-level voltage applied Short-circuit output current3 Supply current (total)
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last. 1989 Feb 05 3
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F674
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to SI/O Output Enable time CS to SI/O Output Disable time CS to SI/O Output Enable time R/W to SI/O Output Disable time R/W to SI/O Waveform 1 Waveform 1 Waveform 3 Waveform 4 Waveform 3 Waveform 4 Waveform 3 Waveform 4 Waveform 3 Waveform 4 80 7.0 6.0 5.5 7.0 3.0 4.5 6.0 7.5 5.0 5.5 TYP 95 9.5 8.5 8.5 9.5 6.0 7.5 8.5 10.0 7.5 8.0 12.5 11.5 11.0 12.5 8.5 10.0 11.5 13.0 10.5 11.0 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 70 6.5 5.5 5.0 6.5 3.0 4.5 5.5 7.0 4.5 5.0 14.0 12.5 12.5 14.0 10.0 11.5 13.0 14.0 12.0 13.5 MAX MHz ns ns ns ns ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(L) th(H) tw(H) tw(L) Setup time, High or Low SI/O to CP Hold time, High or Low SI/O to CP Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low M to CP Hold time, High or Low M to CP Setup time, Low CS to CP Hold time, High CS to CP CP Pulse width, High or Low Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 1 2.0 2.0 1.5 1.5 1.5 1.0 3.0 4.0 2.0 5.5 0.0 0.0 8.0 0.0 3.5 4.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.5 2.5 2.0 2.0 2.0 1.0 3.0 4.0 2.5 6.0 1.0 1.0 9.0 0.0 4.0 5.0 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1989 Feb 05
4
Philips Semiconductors
Product specification
16-bit serial/parallel-in, serial-out shift register (3-State)
74F674
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP VM tW(L) tPLH SI/O VM VM tW(H) tPHL CP VM VM VM VM Dn, CS, M, R/W, SI/O VM ts(H) VM th(H) VM ts(L) VM th(L)
SF01192
SF01193
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Setup and Hold Times
CS, R/W
VM tPZH
VM tPHZ VM 0V VOH -0.3V
CS, R/W
VM tPZL
VM tPLZ VM VOL +0.3V
SI/O
SI/O
SF01194
SF01195
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1989 Feb 05
5

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